US 11,879,933 B2
Method of testing an integrated circuit and testing system
Ankita Patidar, Hsinchu (TW); Sandeep Kumar Goel, Hsinchu (TW); and Yun-Han Lee, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and TSMC NANJING COMPANY, LIMITED, Nanjing (CN)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and TSMC NANJING COMPANY, LIMITED, Jiangsu (CN)
Filed on Aug. 3, 2021, as Appl. No. 17/393,232.
Claims priority of application No. 202110752449.3 (CN), filed on Jul. 2, 2021.
Prior Publication US 2023/0003790 A1, Jan. 5, 2023
Int. Cl. G01R 31/02 (2006.01); G06F 30/398 (2020.01); G01R 31/317 (2006.01); G06F 119/08 (2020.01); G01R 31/28 (2006.01)
CPC G01R 31/2855 (2013.01) [G01R 31/31721 (2013.01); G06F 30/398 (2020.01); G06F 2119/08 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method of testing an integrated circuit on a test circuit board, the integrated circuit including a set of circuit blocks and a first set of heaters, the method comprising:
performing, by a processor, a simulation of a first heat distribution throughout an integrated circuit design, the integrated circuit design being configured to operate at simulated design power levels, and to generate the first heat distribution, and corresponding to the integrated circuit;
manufacturing the integrated circuit according to the integrated circuit design; and
simultaneously performing a burn-in test of the integrated circuit and an automated test of the integrated circuit, the integrated circuit being configured to operate according to the simulated design power levels and being coupled to the test circuit board, wherein the burn-in test has a minimum burn-in temperature of the integrated circuit and a burn-in heat distribution across the integrated circuit.