US 11,879,819 B2
Microfabricated fractionator for particulate matter monitor
Igor Paprotny, Urbana, IL (US); Dorsa Fahimi, Urbana, IL (US); and Omid Mahdavipour, Urbana, IL (US)
Assigned to The Board of Trustees of the University of Illinois, Urbana, IL (US)
Appl. No. 16/348,001
Filed by The Board of Trustees of the University of Illinois, Urbana, IL (US)
PCT Filed Nov. 9, 2017, PCT No. PCT/US2017/060857
§ 371(c)(1), (2) Date May 7, 2019,
PCT Pub. No. WO2018/089631, PCT Pub. Date May 17, 2018.
Claims priority of provisional application 62/419,705, filed on Nov. 9, 2016.
Prior Publication US 2019/0293523 A1, Sep. 26, 2019
Int. Cl. G01N 1/22 (2006.01); G01N 1/24 (2006.01); G01N 15/06 (2006.01); G01N 15/02 (2006.01); G01N 15/00 (2006.01); F04B 43/04 (2006.01); F04B 45/047 (2006.01); F04B 45/04 (2006.01); B01L 3/00 (2006.01); F04B 39/00 (2006.01)
CPC G01N 1/2211 (2013.01) [B01L 3/502761 (2013.01); F04B 39/0027 (2013.01); F04B 43/043 (2013.01); F04B 45/043 (2013.01); F04B 45/047 (2013.01); G01N 1/2205 (2013.01); G01N 1/2273 (2013.01); G01N 1/24 (2013.01); G01N 15/0255 (2013.01); G01N 15/0606 (2013.01); G01N 15/0637 (2013.01); B01L 2200/0652 (2013.01); B01L 2300/0864 (2013.01); G01N 2001/2223 (2013.01); G01N 2015/0046 (2013.01)] 29 Claims
OG exemplary drawing
 
1. A fractionator for a particulate matter (PM) monitor, comprising:
a body defining a vertical air inlet to receive a stream of air from outside the body, the stream of air comprising particles of varying sizes;
a plurality of microfluidic channels within the body, wherein inertial forces within the microfluidic channels are configured to separate the particles by size;
a horizontal air outlet in fluid communication with at least one of the plurality of microfluidic channels for particles having a size below a threshold size; and
a vertical air outlet in fluid communication with at least one of the plurality of microfluidic channels for particles having a size above a threshold size;
wherein the fractionator comprises a first wafer and a second wafer bonded together, wherein each wafer comprises a device layer, a buried oxide (BOX) layer, and a handle layer.