US 12,207,574 B1
Reconfigurable heterojunction memristor, control method, fabrication method and application thereof
Xiaomin Cheng, Hubei (CN); Haobin Li, Hubei (CN); Yunhao Luo, Hubei (CN); and Xiangshui Miao, Hubei (CN)
Assigned to HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY, Hubei (CN)
Filed by HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY, Hubei (CN)
Filed on Jun. 19, 2024, as Appl. No. 18/748,017.
Application 18/748,017 is a continuation of application No. PCT/CN2023/130405, filed on Nov. 8, 2023.
Claims priority of application No. 202311236059.6 (CN), filed on Sep. 22, 2023; and application No. 202311240104.5 (CN), filed on Sep. 22, 2023.
Int. Cl. H10N 70/20 (2023.01); G11C 13/00 (2006.01); G11C 27/00 (2006.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01)
CPC H10N 70/8833 (2023.02) [G11C 13/0007 (2013.01); G11C 27/005 (2013.01); H10B 63/00 (2023.02); H10N 70/026 (2023.02); H10N 70/24 (2023.02); H10N 70/841 (2023.02)] 9 Claims
OG exemplary drawing
 
1. A reconfigurable heterojunction memristor, comprising a substrate, a bottom electrode, a heterojunction intermediate layer, and a top electrode stacked sequentially from bottom to top, wherein
the heterojunction intermediate layer comprises an N-type oxide layer in contact with the bottom electrode and a P-type oxide layer in contact with the top electrode,
the N-type oxide layer is silver peroxide, and the P-type oxide layer is silver oxide;
alternatively, the N-type oxide layer is copper peroxide, and the P-type oxide layer is copper oxide.