| CPC H10B 61/22 (2023.02) [H01L 21/02565 (2013.01); H01L 29/24 (2013.01); H10N 50/01 (2023.02)] | 20 Claims |
|
1. A semiconductor device comprising:
a first dielectric layer over a substrate; and
a first access transistor and a second access transistor in a memory cell of a memory array, the first access transistor and the second access transistor each comprising:
a bottom electrode in the first dielectric layer, wherein the bottom electrode comprises a conductive metal;
a conductive gate in a second dielectric layer, wherein the second dielectric layer is over the bottom electrode and the first dielectric layer;
a channel region extending through the conductive gate to be in physical contact with the bottom electrode; and
a top electrode over the channel region;
a magnetic tunnel junction (MTJ) disposed between the first access transistor and the second access transistor, wherein the MTJ does not overlap the channel region of the first access transistor or the channel region of the second access transistor; and
an isolation structure disposed between the first access transistor and the second access transistor, wherein a bottom surface of the channel region of the first access transistor and a bottom surface of the channel region of the second access transistor are below a bottom surface of the isolation structure, and wherein the bottom surface of the isolation structure is in physical contact with the bottom electrode of the first access transistor.
|