US 12,207,476 B2
Memory cell with unipolar selectors
Katherine H. Chiang, New Taipei (TW); Chung-Te Lin, Tainan (TW); and Mauricio Manfrini, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 17, 2023, as Appl. No. 18/353,290.
Application 18/353,290 is a continuation of application No. 17/411,451, filed on Aug. 25, 2021, granted, now 11,778,836.
Application 17/411,451 is a continuation of application No. 16/531,482, filed on Aug. 5, 2019, granted, now 11,107,859, issued on Aug. 31, 2021.
Prior Publication US 2023/0363180 A1, Nov. 9, 2023
Int. Cl. G11C 11/16 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01)
CPC H10B 61/10 (2023.02) [G11C 11/161 (2013.01); G11C 11/1657 (2013.01); G11C 11/1659 (2013.01); G11C 11/1675 (2013.01); H10N 50/01 (2023.02); H10N 50/80 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a magnetic tunnel junction (MTJ) disposed on a first electrode within a dielectric structure over a substrate;
a first unipolar selector disposed within the dielectric structure and electrically coupled to the first electrode;
a second unipolar selector disposed within the dielectric structure and electrically coupled to the first electrode; and
wherein the first unipolar selector laterally extends between a first vertical line intersecting the MTJ and the substrate and a second vertical line intersecting the second unipolar selector and the substrate.