US 12,207,474 B2
Stacked ferroelectric structure
Rainer Yen-Chieh Huang, Hsinchu (TW); Hai-Ching Chen, Hsinchu (TW); and Chung-Te Lin, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Nov. 15, 2022, as Appl. No. 17/987,066.
Application 17/987,066 is a division of application No. 17/184,856, filed on Feb. 25, 2021, granted, now 11,508,755.
Prior Publication US 2023/0074585 A1, Mar. 9, 2023
Int. Cl. H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H10B 51/30 (2023.01)
CPC H10B 51/30 (2023.02) [H01L 29/40111 (2019.08); H01L 29/516 (2013.01); H01L 29/6684 (2013.01); H01L 29/78391 (2014.09)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) comprising a memory structure, wherein the memory structure comprises:
a first electrode; and
a ferroelectric structure vertically stacked with the first electrode, wherein the ferroelectric structure comprises:
a first ferroelectric layer;
a second ferroelectric layer overlying the first ferroelectric layer; and
a first restoration layer between and directly contacting the first and second ferroelectric layers, wherein the first restoration layer is a different material type than that of the first and second ferroelectric layers, and wherein the first and second ferroelectric layers have a same material composition.