CPC H10B 43/40 (2023.02) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/544 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H01L 2223/54426 (2013.01)] | 18 Claims |
1. A memory device, comprising:
a stack structure comprising tiers respectively including conductive material and insulative material vertically adjacent the conductive material;
an array of cell pillar structures vertically extending through the stack structure;
an inverted staircase structure comprising horizontal ends of at least some of the tiers of the stack structure, relatively vertically higher steps of the inverted staircase structure horizontally positioned farther away from the array of cell pillar structures than relatively vertically lower steps of the inverted staircase structure;
a conductive routing tier vertically underlying the stack structure and comprising conductive line structures coupled to the array of cell pillar structures;
lateral contact structures vertically overlying the stack structure and coupled to the array of cell pillar structures;
an insulative structure vertically overlying and horizontally overlapping the lateral contact structures, the array of cell pillar structures vertically extending through the lateral contact structures to the insulative structure;
additional insulative structures horizontally neighboring the insulative structure, at least some of the contact structures horizontally overlapping the additional insulative structures;
control logic circuitry vertically overlying the lateral contact structures; and
contact structures coupled to the control logic circuitry and vertically extending from the control logic circuitry to the conductive routing tier.
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