US 12,207,469 B2
Vertical memory devices and methods of manufacturing the same
Junhyoung Kim, Seoul (KR); Seonho Yoon, Hwaseong-si (KR); and Bonghyun Choi, Yongin-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Nov. 1, 2023, as Appl. No. 18/386,112.
Application 18/386,112 is a division of application No. 17/567,364, filed on Jan. 3, 2022, granted, now 11,818,889.
Application 17/567,364 is a continuation of application No. 16/850,097, filed on Apr. 16, 2020, granted, now 11,217,603, issued on Jan. 4, 2022.
Claims priority of application No. 10-2019-0095919 (KR), filed on Aug. 7, 2019.
Prior Publication US 2024/0064981 A1, Feb. 22, 2024
Int. Cl. H10B 43/27 (2023.01); H01L 23/522 (2006.01); H10B 41/27 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 23/5226 (2013.01); H10B 41/27 (2023.02)] 17 Claims
OG exemplary drawing
 
1. A method of manufacturing a vertical memory device, the method comprising:
alternately and repeatedly stacking insulation layers and sacrificial layers along a first direction to form a mold layer on a substrate, the first direction being substantially vertical to an upper surface of the substrate, and the substrate including:
a cell region,
a through via region formed on each of two opposite sides of the cell region,
a mold region surrounding the cell region and the through via region, and
a scribe lane (S/L) region surrounding the mold region;
removing a portion of the mold layer formed on the through via region, the cell region and the mold region to form a first mold and a second mold, wherein the first mold is formed on both the mold region and the S/L region and the second mold is formed on the cell region;
forming a channel extending through the second mold;
forming an opening extending through the second mold; and
replacing each of the sacrificial layers in the second mold with gate electrodes through the opening.