| CPC H10B 43/27 (2023.02) [H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] | 20 Claims |
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1. A semiconductor memory device, comprising:
a cell unit including a stack structure and a channel structure penetrating through the stack structure, the stack structure being on a substrate, the stack structure extending in a first direction, the stack structure including at least one string selection gate and a plurality of cell gates;
a plurality of cell separation structures separating the cell unit in the first direction; and
a plurality of gate cutting structures defining regions within the cell unit between adjacent cell separation structures of the plurality of cell separation structures,
wherein the cell unit includes
a first region defined between a first cell separation structure of the plurality of cell separation structures and a first gate cutting structure of the plurality of gate cutting structures, and
a second region defined between the first gate cutting structure and a second gate cutting structure of the plurality of gate cutting structures, the first and second gate cutting structures being adjacent gate cutting structures, and
wherein a ratio of a region of the at least one string selection gate that is occupied by a conductive material in the second region is greater than a ratio of a region of at least one cell gate of the plurality of cell gates that is occupied by the conductive material in the second region.
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