US 12,207,461 B2
Tier expansion offset
Li Cheng, Liaoning (CN)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 21, 2021, as Appl. No. 17/558,001.
Prior Publication US 2023/0200061 A1, Jun. 22, 2023
Int. Cl. H10B 41/40 (2023.01); H10B 41/20 (2023.01); H10B 41/35 (2023.01); H10B 41/50 (2023.01); H10B 43/40 (2023.01); H10B 43/50 (2023.01); G11C 5/02 (2006.01); G11C 11/408 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01)
CPC H10B 41/35 (2023.02) [H10B 41/20 (2023.02); H10B 41/40 (2023.02); H10B 41/50 (2023.02); H10B 43/40 (2023.02); H10B 43/50 (2023.02); G11C 5/025 (2013.01); G11C 11/4085 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a substrate;
a memory block located on top of the substrate, the memory block comprising:
a staircase area having a first height; and
a memory array area located adjacent the staircase area, the memory array area comprising a plurality of memory pillars extending into the memory block, wherein the memory array area has a second height different than the first height, and wherein a tier expansion height is a non-zero difference between the second height and the first height; and
a pre-offset platform located between the substrate and the staircase area of the memory block, wherein a lowermost layer of the memory array area has a lowermost surface that is coplanar with a lowermost surface of the pre-offset platform, and wherein the pre-offset platform is oriented and arranged to offset the tier expansion height so that an upper surface of the staircase area and an upper surface of the memory array area are located in a same plane.