US 12,207,457 B2
Semiconductor devices and methods of manufacturing the same
Yanghee Lee, Incheon (KR); Jonghyuk Park, Suwon-si (KR); Ilyoung Yoon, Hwaseong-si (KR); Boun Yoon, Suwon-si (KR); and Heesook Cheon, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jan. 16, 2024, as Appl. No. 18/413,434.
Application 18/413,434 is a continuation of application No. 17/859,247, filed on Jul. 7, 2022, granted, now 11,910,594.
Application 17/859,247 is a continuation of application No. 16/903,040, filed on Jun. 16, 2020, granted, now 11,411,004, issued on Aug. 9, 2022.
Claims priority of application No. 10-2019-0136634 (KR), filed on Oct. 30, 2019.
Prior Publication US 2024/0155830 A1, May 9, 2024
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/37 (2023.02) [H10B 12/0387 (2023.02); H10B 12/482 (2023.02); H10B 12/50 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
forming a plurality of first structures and a plurality of key structures on a first region and a second region, respectively, of a substrate, the second region surrounding the first region, the plurality of first structures being spaced apart from each other by a first trench, and the plurality of key structures being spaced apart from each other by a second trench;
forming a first filling layer on the plurality of first structures and the plurality of key structures to fill the first trench and the second trench, wherein the first filling layer has a first height difference among portions of the first filling layer;
performing a melting process on the first filling layer to form a second filling layer, wherein the second filling layer has a second height difference among portions of the second filling layer, the second height difference being smaller than the first height difference;
planarizing the second filling layer until upper surfaces of the plurality of first structures and the plurality of key structures are exposed to form first and second filling patterns between the plurality of first structures and between the plurality of key structures, respectively;
removing upper portions of the first and second filling patterns;
forming a conductive layer on the first and second filling patterns, the plurality of first structures, and the plurality of key structures;
planarizing the conductive layer to form a planarized conductive layer; and
patterning a first portion of the planarized conductive layer on the first region of the substrate using a second portion of the planarized conductive layer on the second filling pattern as an overlay key,
wherein the second portion of the planarized conductive layer includes an upper surface defining a third trench as the overlay key.