US 12,207,395 B2
Backplane footprint for high speed, high density electrical connectors
Marc Robert Charbonneau, Bedford, NH (US); and Jose Ricardo Paniagua, Newmarket, NH (US)
Assigned to Amphenol Corporation, Wallingford, CT (US)
Filed by Amphenol Corporation, Wallingford, CT (US)
Filed on Sep. 27, 2023, as Appl. No. 18/475,344.
Application 18/475,344 is a division of application No. 17/872,082, filed on Jul. 25, 2022, granted, now 11,805,595.
Application 17/218,335 is a division of application No. 16/666,536, filed on Oct. 29, 2019, granted, now 10,993,314, issued on Apr. 27, 2021.
Application 16/666,536 is a division of application No. 16/214,298, filed on Dec. 10, 2018, granted, now 10,485,097, issued on Nov. 19, 2019.
Application 16/214,298 is a division of application No. 15/452,096, filed on Mar. 7, 2017, granted, now 10,187,972, issued on Jan. 22, 2019.
Application 17/872,082 is a continuation of application No. 17/218,335, filed on Mar. 31, 2021, granted, now 11,553,589, issued on Jan. 10, 2023.
Claims priority of provisional application 62/305,049, filed on Mar. 8, 2016.
Prior Publication US 2024/0023232 A1, Jan. 18, 2024
Int. Cl. H05K 1/02 (2006.01); H01R 12/51 (2011.01); H01R 12/55 (2011.01); H01R 12/70 (2011.01); H01R 12/71 (2011.01); H01R 12/72 (2011.01); H01R 12/73 (2011.01); H01R 13/514 (2006.01); H01R 13/516 (2006.01); H01R 13/6461 (2011.01); H01R 13/6467 (2011.01); H01R 13/6471 (2011.01); H01R 13/6474 (2011.01); H01R 13/6585 (2011.01); H01R 13/6587 (2011.01); H05K 1/03 (2006.01); H05K 1/09 (2006.01); H05K 1/11 (2006.01); H05K 1/18 (2006.01); H05K 3/04 (2006.01); H05K 3/20 (2006.01); H05K 3/30 (2006.01); H05K 3/32 (2006.01); H05K 3/40 (2006.01); H05K 3/42 (2006.01); H05K 3/46 (2006.01)
CPC H05K 1/0245 (2013.01) [H01R 12/7082 (2013.01); H01R 12/716 (2013.01); H05K 1/0219 (2013.01); H05K 1/0251 (2013.01); H05K 1/115 (2013.01); H05K 3/429 (2013.01); H05K 1/0225 (2013.01); H05K 2201/096 (2013.01); H05K 2201/09727 (2013.01); H05K 2201/09845 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A printed circuit board comprising:
a plurality of layers including conductive layers separated by dielectric layers; and
a connector footprint formed on the plurality of layers, the connector footprint comprising:
a plurality of columns of pairs of signal vias, the pairs of signal vias in adjacent columns of the plurality of columns being offset in a direction of the columns; and
at least one shadow via disposed in the columns between adjacent pairs of signal vias, wherein the at least one shadow via is plated or filled with a conductive material.