| CPC H03K 5/1565 (2013.01) [G06F 1/12 (2013.01); G11C 11/4076 (2013.01); H03K 5/131 (2013.01); H03K 5/135 (2013.01); H03L 7/0812 (2013.01); H03K 2005/00058 (2013.01)] | 12 Claims |
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7. A duty cycle monitoring apparatus for a memory interface, comprising:
an offset generator for receiving a clock signal as input and generating a first delay time offset and a second delay time offset;
a first delay circuit for receiving the clock signal and the first delay time offset and then outputting a first delayed signal;
a second delay circuit for receiving the first delayed signal and the second delay time offset and then outputting a second delayed signal;
a delay-locked loop for receiving the clock signal and the second delayed signal and then outputting a delay value corresponding to a half-period of the clock signal; and
a monitoring circuit for monitoring, based on the first delayed signal, whether a duty cycle of the clock signal conforms to a duty cycle specification.
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