US 12,206,419 B2
Delay-locked loop circuit and method
Chung-Peng Hsieh, Hsinchu (TW); Chih-Chiang Chang, Hsinchu (TW); and Yung-Chow Peng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Dec. 1, 2023, as Appl. No. 18/526,226.
Application 18/526,226 is a continuation of application No. 18/155,906, filed on Jan. 18, 2023, granted, now 11,855,644.
Application 18/155,906 is a continuation of application No. 17/376,389, filed on Jul. 15, 2021, granted, now 11,563,429, issued on Jan. 24, 2023.
Application 17/376,389 is a continuation of application No. 17/030,160, filed on Sep. 23, 2020, granted, now 11,082,035, issued on Aug. 3, 2021.
Claims priority of provisional application 63/012,980, filed on Apr. 21, 2020.
Prior Publication US 2024/0106425 A1, Mar. 28, 2024
Int. Cl. H03K 5/14 (2014.01); H03K 5/131 (2014.01); H03K 5/134 (2014.01); H03K 5/24 (2006.01)
CPC H03K 5/14 (2013.01) [H03K 5/131 (2013.01); H03K 5/134 (2014.07); H03K 5/2481 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A delay-locked loop (DLL) circuit comprising:
a phase detector;
a low pass filter comprising an input terminal coupled to an output terminal of the phase detector; and
a digitally controlled delay line (DCDL) coupled to the low pass filter, the DCDL comprising:
an input terminal;
an output terminal coupled to an input terminal of the phase detector; and
a plurality of stages configured to propagate a signal along a first signal path from the input terminal to a selectable return stage of the plurality of stages, and along a second signal path from the return stage of the plurality of stages to the output terminal, each stage of the plurality of stages comprising:
a first inverter configured to selectively propagate the signal along the first signal path;
a second inverter configured to selectively propagate the signal along the second signal path;
a third inverter configured to selectively propagate the signal from the first signal path to the second signal path; and either:
a fourth inverter configured to selectively propagate the signal along the first signal path and a fifth inverter configured to selectively propagate the signal along the second signal path, or
a sixth inverter configured to selectively propagate the signal from the first signal path to the second signal path.