US 12,206,377 B2
Impedance matching circuit, method for impedance matching and semiconductor memory
Yifan Ji, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Feb. 14, 2023, as Appl. No. 18/168,640.
Application 18/168,640 is a continuation of application No. PCT/CN2022/112130, filed on Aug. 12, 2022.
Claims priority of application No. 202210927224.1 (CN), filed on Aug. 3, 2022.
Prior Publication US 2024/0048126 A1, Feb. 8, 2024
Int. Cl. G11C 11/40 (2006.01); G11C 11/4093 (2006.01); H03H 11/28 (2006.01); H03K 5/24 (2006.01); H03K 17/687 (2006.01); H03K 19/20 (2006.01)
CPC H03H 11/28 (2013.01) [G11C 11/4093 (2013.01); H03K 5/24 (2013.01); H03K 17/6872 (2013.01); H03K 19/20 (2013.01); G11C 2207/2254 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An impedance matching circuit, the impedance matching circuit comprising a driver circuit, a calibration circuit, a digital logic circuit, a receiving circuit and a first resistor, wherein an output of the driver circuit is connected to the receiving circuit, an output of the calibration circuit is connected to the first resistor,
wherein the calibration circuit is configured to cooperate with the driver circuit to perform calibration according to impedance values of the first resistor and the receiving circuit, to determine a plurality of calibration parameters at different output level values,
wherein the digital logic circuit is configured to receive the plurality of calibration parameters and determine a target calibration parameter of each of at least one transistor slice in the driver circuit, and
wherein the driver circuit is configured to receive the target calibration parameter, and perform impedance adjustment on the at least one transistor slice according to the target calibration parameter, to form an impedance matching relationship between an impedance value of the driver circuit and the impedance value of the receiving circuit at different output level values.