1-a) providing a transparent insulating substrate, wherein a material for the transparent insulating substrate has a bandgap greater than 5.0 eV and does not absorb ultraviolet light with a wavelength greater than 250 nm; and

1-b) providing an n-type conductive monocrystalline silicon wafer with a resistivity less than 0.01 ohm·cm; performing polishing on one side of the n-type conductive monocrystalline silicon wafer to form a polished surface, thinning a non-polished surface of the n-type conductive monocrystalline silicon wafer, and attaching the n-type conductive monocrystalline silicon wafer onto the transparent insulating substrate, with the polished surface facing upwards, to form the composite conductive substrate, wherein an outer periphery of the n-type conductive monocrystalline silicon wafer has a same shape as an outer periphery of the transparent insulating substrate;

3-a) overlaying the insulating template onto the composite conductive substrate in a completely aligned manner;

3-b) preparing a protective layer on the insulating template, such that the protective layer is formed on the n-type conductive monocrystalline silicon wafer in areas corresponding to the circular through holes of the insulating template, while no protective layer is formed in areas not corresponding to the circular through holes of the insulating template;

3-c) removing the insulating template, and performing ion implantation on the n-type conductive monocrystalline silicon wafer, such that ions are implanted into the areas of the n-type conductive monocrystalline silicon wafer which are not covered by the protective layer, thereby increasing resistivity and making the areas electrically insulating;

3-d) performing chemical cleaning on the composite conductive substrate after ion implantation to remove the protective layer, wherein the areas corresponding to the circular through holes of the insulating template remain conductive, while remaining areas become electrically insulating, thus completing modification of the n-type conductive monocrystalline silicon wafer to obtain the template substrate; and

3-e) corresponding to the insulating template, providing a plurality of pixel regions arranged closely in a two-dimensional manner on the n-type conductive monocrystalline silicon wafer of the template substrate, wherein each of the pixel regions comprises four circular conductive regions, namely, two red-light conductive regions, one green-light conductive region, and one blue-light conductive region, and the rest being an insulating region;

4-a) providing monocrystalline graphene, wherein an outer periphery of the monocrystalline graphene has a same shape as the template substrate, and the monocrystalline graphene has a thickness of 3 to 6 atomic layers;

4-b) overlaying the monocrystalline graphene onto the template substrate in a completely aligned manner;

4-c) overlaying the insulating template onto the monocrystalline graphene in a completely aligned manner, wherein the one green-light region through hole, the one blue-light region through hole, and the two red-light region through holes in each of the through hole units of the insulating template are respectively precisely aligned with the one green-light conductive region, the one blue-light conductive region, and the two red-light conductive regions in each of the pixel regions of the n-type conductive monocrystalline silicon wafer;

4-d) thinning the monocrystalline graphene in areas corresponding to blue-light region through holes and green-light region through holes, until the areas have a thickness of one atomic layer;

4-e) performing uniform nitrogen atom doping on the monocrystalline graphene in areas corresponding to the blue-light region through holes, the green-light region through holes, and red-light region through holes, wherein the monocrystalline graphene after the uniform nitrogen atom doping exhibits ultraviolet absorption within a range of 240 nm to 270 nm;

4-f) depositing an AlON layer on the monocrystalline graphene in areas corresponding to the blue-light region through holes, such that a nitride epitaxial layer grown thereon has a metal lattice polarity; and

4-g) cutting edges of the monocrystalline graphene that correspond to the blue-light region through holes, the green-light region through holes, and the red-light region through holes of the insulating template, wherein the cutting is performed only on the monocrystalline graphene; and removing the insulating template to obtain the customized template graphene substrate,

wherein a multiple quantum well (MQW) of the vertical-structure all-nitride material comprises multiple periods of InGaN potential wells and GaN potential barriers;

due to the different surface properties of the blue-region graphene array elements, the green-region graphene array elements, and the red-region graphene array elements on the customized template graphene substrate, vertical-structure all-nitride materials grown thereon have different lattice polarities, stress states, and In compositions in MQW structures, and thereby different central emission wavelengths, and therefore a vertical-structure monocrystalline metal-polar blue-light-emitting nitride, a vertical-structure monocrystalline nitrogen-polar green-light-emitting nitride, and a vertical-structure monocrystalline stress-relaxed nitrogen-polar red-light-emitting nitride are grown respectively on the blue-region graphene array elements, the green-region graphene array elements, and the red-region graphene array elements, to form a blue-light-emitting micro-LED, a green-light-emitting micro-LED, and a red-light-emitting micro-LED, as well as an area without micro-LEDs, which constitute a micro-LED pixel unit; and

the blue-light-emitting micro-LED, the green-light-emitting micro-LED, and the red-light-emitting micro-LED are micrometer-sized pillars;