US 12,206,005 B2
Semiconductor structures and methods thereof
Chung-Wei Hsu, Hsinchu County (TW); Kuo-Cheng Chiang, Hsinchu County (TW); Mao-Lin Huang, Hsinchu (TW); Lung-Kun Chu, New Taipei (TW); Jia-Ni Yu, New Taipei (TW); Kuan-Lun Cheng, Hsin-Chu (TW); and Chih-Hao Wang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDICTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 28, 2023, as Appl. No. 18/361,665.
Application 18/361,665 is a continuation of application No. 17/228,922, filed on Apr. 13, 2021, granted, now 11,728,401.
Claims priority of provisional application 63/107,887, filed on Oct. 30, 2020.
Prior Publication US 2023/0378302 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/423 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/42392 (2013.01) [H01L 21/823807 (2013.01); H01L 21/823828 (2013.01); H01L 27/092 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a semiconductor substrate;
a semiconductor layer over and separated from the semiconductor substrate;
an isolation structure over the semiconductor substrate;
a dielectric fin extending from the isolation structure and extending above the semiconductor layer;
a gate dielectric layer wrapping around the semiconductor layer; and
a first gate electrode layer over the gate dielectric layer, wherein the first gate electrode layer includes a first section wrapping around the semiconductor layer and a second section on a sidewall surface of the dielectric fin, the second section having a top surface that is lower than a top surface of the dielectric fin;
wherein in a top view, the dielectric fin is parallel to and spaced a distance from source/drain regions disposed on either side of the semiconductor layer.