CPC H01L 29/42392 (2013.01) [H01L 29/0673 (2013.01); H01L 29/66545 (2013.01); H01L 29/785 (2013.01); H01L 29/78696 (2013.01); H01L 2029/7858 (2013.01)] | 20 Claims |
1. A method, comprising:
forming a p-well and an n-well in a substrate;
forming a stack of interleaving first semiconductor material layers and second semiconductor material layers over the p-well and the n-well, the first semiconductor material layers having a first thickness and the second semiconductor material layers having a second thickness that is different than the first thickness;
annealing the stack of interleaving semiconductor layers;
patterning the stack to form fin-shaped structures including a first fin-shaped structure over the n-well and a second fin-shaped structure over the p-well;
performing an etching process to remove the second semiconductor material layers from the first and second fin-shaped structures, wherein the first semiconductor material layers have a different thickness within each of the first and second fin-shaped structures after the etching process; and
forming a metal gate over the first and second fin-shaped structures.
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