US 12,205,982 B2
Trench pattern for trench capacitor yield improvement
Yuan-Sheng Huang, Taichung (TW); and Yi-Chen Chen, Jhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Nov. 17, 2023, as Appl. No. 18/512,096.
Application 18/512,096 is a continuation of application No. 18/076,780, filed on Dec. 7, 2022, granted, now 11,855,133.
Application 18/076,780 is a continuation of application No. 17/140,374, filed on Jan. 4, 2021, granted, now 11,545,543, issued on Jan. 3, 2023.
Claims priority of provisional application 63/106,028, filed on Oct. 27, 2020.
Prior Publication US 2024/0088210 A1, Mar. 14, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/66 (2006.01); H01L 29/94 (2006.01); H01L 49/02 (2006.01)
CPC H01L 28/91 (2013.01) [H01L 28/90 (2013.01); H01L 29/66181 (2013.01); H01L 29/945 (2013.01); H01L 28/40 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a substrate; and
a trench capacitor on the substrate and comprising a plurality of capacitor segments extending into the substrate;
wherein the plurality of capacitor segments comprises a first capacitor segment and a second capacitor segment,
the plurality of capacitor segments are spaced from each other along an axis,
the first capacitor segment has a width different than a width of the second capacitor segment,
the first and second capacitor segments have individual top layouts with greatest dimensions extending transverse to the axis and the width of the first capacitor segment,
the substrate has a first sidewall and a second sidewall respectively facing and bordering the first and second capacitor segments, and
a height of the first sidewall is substantially the same as a height of the second sidewall.