US 12,205,915 B2
Microelectronic package with solder array thermal interface material (SA-TIM)
Debendra Mallik, Chandler, AZ (US); Sergio Antonio Chan Arguedas, Chandler, AZ (US); Jimin Yao, Chandler, AZ (US); and Chandra Mohan Jha, Tempe, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 3, 2023, as Appl. No. 18/346,321.
Application 18/346,321 is a continuation of application No. 16/451,754, filed on Jun. 25, 2019, granted, now 11,735,552.
Prior Publication US 2023/0343738 A1, Oct. 26, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); H01L 23/16 (2006.01); H01L 23/367 (2006.01)
CPC H01L 24/17 (2013.01) [H01L 23/16 (2013.01); H01L 23/3675 (2013.01); H01L 23/562 (2013.01); H01L 2224/17051 (2013.01); H01L 2224/1713 (2013.01); H01L 2224/17163 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/17519 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A microelectronic package, comprising:
a package substrate;
a die coupled with the package substrate at a first face of the die;
a plurality of solder thermal interface material (STIM) thermal interconnects coupled with the die at a second face of the die, wherein the second face is opposite the first face;
an integrated heat spreader (IHS) coupled with the plurality of STIM thermal interconnects, wherein a first STIM thermal interconnect of the plurality of STIM thermal interconnects has a different size or shape than a second STIM thermal interconnect of the plurality of STIM thermal interconnects; and
a thermal underfill material positioned between the IHS and the die, wherein the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects.