US 12,205,903 B2
Semiconductor package and manufacturing method thereof
Yung-Chi Chu, Kaohsiung (TW); Hung-Jui Kuo, Hsinchu (TW); Jhih-Yu Wang, New Taipei (TW); and Yu-Hsiang Hu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Oct. 5, 2023, as Appl. No. 18/481,961.
Application 17/705,409 is a division of application No. 16/009,208, filed on Jun. 15, 2018, granted, now 11,289,426, issued on Mar. 29, 2022.
Application 18/481,961 is a continuation of application No. 17/705,409, filed on Mar. 28, 2022, granted, now 11,798,893.
Prior Publication US 2024/0038674 A1, Feb. 1, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/58 (2006.01)
CPC H01L 23/5389 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/4864 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/3121 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 23/562 (2013.01); H01L 23/564 (2013.01); H01L 23/585 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 2221/68372 (2013.01); H01L 2224/214 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A package, comprising:
a die wrapped around by an encapsulant; and
a redistribution structure disposed over the die and the encapsulant, wherein the redistribution structure comprises:
a conductive via connected with the die, wherein the conductive via has a vertical sidewall;
a routing layer located above and connected with the conductive via;
a seal ring structure disposed on the encapsulant, wherein the seal ring structure comprises a first seal ring element and a second seal ring element located above the first seal ring element, the second seal ring element includes a seed layer in contact with a top surface of the first seal ring element; and
a first dielectric layer and a second dielectric layer located above the first dielectric layer, wherein the first seal ring element and the conductive via are wrapped around by the first dielectric layer, the second seal ring element and the routing layer are wrapped around by the second dielectric layer.