US 12,205,868 B2
Oversized via as through-substrate-via (TSV) stop layer
Min-Feng Kao, Chiayi (TW); Dun-Nian Yaung, Taipei (TW); Hsing-Chih Lin, Tainan (TW); Jen-Cheng Liu, Hsin-Chu (TW); Yi-Shin Chu, Hsinchu (TW); and Ping-Tzu Chen, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 20, 2023, as Appl. No. 18/355,463.
Application 18/355,463 is a continuation of application No. 17/696,357, filed on Mar. 16, 2022, granted, now 11,756,862.
Application 17/696,357 is a continuation of application No. 16/898,647, filed on Jun. 11, 2020, granted, now 11,282,769, issued on Mar. 22, 2022.
Prior Publication US 2023/0361005 A1, Nov. 9, 2023
Int. Cl. H01L 29/40 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/481 (2013.01) [H01L 21/76898 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06544 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip structure, comprising:
a first via disposed within a dielectric structure on a substrate;
a second via disposed within the dielectric structure and laterally separated from the first via by the dielectric structure, wherein the first via has a first width that is smaller than a second width of the second via;
an interconnect wire vertically contacting the second via and extending laterally past an outermost sidewall of the second via;
a through-substrate via (TSV) arranged over the second via and extending through the substrate, wherein the TSV has a minimum width that is smaller than the second width of the second via; and
wherein the second via has opposing outermost sidewalls that are laterally outside of the TSV.