	US 12,205,853 B2
	Integrated circuit test method and structure thereof
Hsien-Wen Liu, Hsinchu (TW); and Hsien-Wei Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 26, 2022, as Appl. No. 17/873,804.
Application 17/873,804 is a division of application No. 17/195,537, filed on Mar. 8, 2021, granted, now 11,532,524.
Claims priority of provisional application 63/056,924, filed on Jul. 27, 2020.
Prior Publication US 2022/0367296 A1, Nov. 17, 2022
Int. Cl. H01L 21/66 (2006.01); H01L 23/00 (2006.01)

CPC H01L 22/14 (2013.01) [H01L 22/20 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/13 (2013.01); H01L 24/32 (2013.01); H01L 2224/03001 (2013.01); H01L 2224/0392 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05073 (2013.01); H01L 2224/05082 (2013.01); H01L 2224/05083 (2013.01); H01L 2224/05084 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05564 (2013.01); H01L 2224/05573 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05655 (2013.01); H01L 2224/05666 (2013.01); H01L 2224/05686 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/13007 (2013.01); H01L 2224/32145 (2013.01)]

20 Claims

1. A semiconductor device comprising:

a semiconductor die that includes a device layer, an interconnect layer over the device layer, a conductive pad over the interconnect layer, a conductive seed layer directly on the conductive pad, and a passivation layer encapsulating the conductive pad and the conductive seed layer, wherein the conductive pad is between the interconnect layer and the conductive seed layer, wherein a conductive feature lands on the conductive pad and is free from a physical interface with the conductive seed layer, wherein the conductive seed layer is smaller than the conductive pad from a top view.