	US 12,205,848 B2
	FinFET gate structure and related methods
Cheng-Ting Chung, Hsinchu (TW); Ching-Wei Tsai, Hsinchu (TW); and Kuan-Lun Cheng, Hsin-Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jan. 4, 2022, as Appl. No. 17/568,114.
Application 17/568,114 is a division of application No. 16/449,014, filed on Jun. 21, 2019, granted, now 11,217,484.
Claims priority of provisional application 62/753,695, filed on Oct. 31, 2018.
Prior Publication US 2022/0122890 A1, Apr. 21, 2022
Int. Cl. H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01)

CPC H01L 21/823431 (2013.01) [H01L 21/823418 (2013.01); H01L 21/823437 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 29/66545 (2013.01); H01L 29/6656 (2013.01)]

20 Claims

1. A semiconductor device, comprising:

a substrate including a fin element extending therefrom;

a gate structure formed over the fin element, wherein the gate structure includes a dielectric layer on the fin element, a metal capping layer disposed over the dielectric layer, and a metal electrode formed over the metal capping layer; and

first sidewall spacers formed on opposing sidewalls of the metal capping layer and the metal electrode;

wherein the dielectric layer includes an interfacial layer formed over the fin element and a high-K dielectric layer formed over the interfacial layer, and wherein the interfacial layer and the high-K dielectric layer extend laterally underneath the first sidewall spacers to form a dielectric footing region.