US 12,205,816 B2
Interconnect structure for semiconductor devices
Po-Chuan Wang, Taipei (TW); Guan-Xuan Chen, Taoyuan (TW); Chia-Yang Hung, Kaohsiung (TW); Sheng-Liang Pan, Hsinchu (TW); and Huan-Just Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 16, 2021, as Appl. No. 17/232,465.
Claims priority of provisional application 63/085,217, filed on Sep. 30, 2020.
Prior Publication US 2022/0102138 A1, Mar. 31, 2022
Int. Cl. H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01)
CPC H01L 21/02063 (2013.01) [H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/76814 (2013.01); H01L 21/76883 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor device, the method comprising:
forming a first conductive feature in a first dielectric layer disposed over a substrate;
forming a second dielectric layer over the first dielectric layer;
etching the second dielectric layer using a patterned mask layer to form an opening in the second dielectric layer, wherein the opening exposes the first conductive feature, wherein etching the second dielectric layer comprises etching the second dielectric layer by performing a first plasma process, wherein the first plasma process is performed using a gas source comprising fluoride;
removing the patterned mask layer by performing an ashing process after the etching, wherein performing the ashing process comprises performing a second plasma process different from the first plasma process, wherein the second plasma process is performed using a gas source comprising hydrogen, wherein a first plasma of the first plasma process is different from a second plasma of the second plasma process;
wet cleaning the opening after the ashing process, wherein the wet cleaning enlarges a bottom portion of the opening; and
filling the enlarged opening with a first electrically conductive material.