| CPC G11C 8/18 (2013.01) [G06F 1/12 (2013.01); G06F 13/20 (2013.01); G11C 7/222 (2013.01)] | 20 Claims |
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1. A circuit comprising:
a set of data paths operatively coupled to a Double Data Rate (DDR) Dynamic Random-Access Memory (DRAM) memory device and configured to provide data signals that carry data bits read from the DDR DRAM memory device; and
a read data strobe (RDQS) path operatively coupled to the DDR DRAM memory device and configured to provide data strobe signals for sampling the data bits from the data signals provided by the set of data paths, the RDQS path comprising a plurality of delay line components configured to adjust the RDQS signal at a center of the data bits carried by the data signals, the plurality of delay line components comprising:
a first digital delay line component operatively coupled to an output of the DDR DRAM memory device that provides a RDQS signal, the first digital delay line component being configured to provide skew between the data signals and the RDQS signal;
a plurality of second digital delay line components operatively coupled to an output of the first digital delay line component, an individual second digital delay line component of the plurality of second digital delay line components being configured to provide de-skewing between an output signal provided by the first digital delay line component and a data signal provided by an individual data path in the set of data paths that corresponds to the individual second digital delay line component;
a plurality of third digital delay line components operatively coupled to outputs of the plurality of second digital delay line components, an individual third digital delay line component of the plurality of third digital delay line components being configured to output a rising-edge RDQS signal for sampling data bits from the data signal provided by the individual data path; and
a plurality of fourth digital delay line components operatively coupled to the outputs of the plurality of second digital delay line components, an individual fourth digital delay line component of the plurality of fourth digital delay line components being configured to output a falling-edge RDQS signal for sampling data bits from the data signal provided by the individual data path, the individual third digital delay line component and the individual fourth digital delay line component create offset between the rising-edge RDQS signal and the falling-edge RDQS signal to compensate for duty cycle distortion by creating offset.
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