| CPC G11C 7/1096 (2013.01) [G06F 7/4824 (2013.01); G06N 3/063 (2013.01); G11C 7/1069 (2013.01); G11C 7/12 (2013.01); G11C 8/08 (2013.01)] | 20 Claims |
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1. A memory system for performing a computing-in-memory (CiM) operation, the memory system comprising:
a memory array comprising a plurality of memory cells, the memory cells being coupled to a bit line and respectively controlled by a plurality of word lines; and
a processing circuit coupled to the memory array, the processing circuit comprising:
a programming circuit coupled to the memory array and configured to perform a write operation for programming electrical characteristics of the memory cells; and
a control circuit coupled to the programming circuit and configured to:
receive a plurality of weight data corresponding to a plurality of weight values; and
control the write operation performed by the programming circuit, so the electrical characteristics of the memory cells are programmed following a sequential order of the weight values;
a readout circuit coupled to the control circuit and configured to perform a read operation on the memory cells, for reading the electrical characteristics of the memory cells to generate a first summation result corresponding to a sum of products of a plurality of input values multiplied by the weight values; and
a shift converter coupled to the readout circuit and configured to generate a signed summation result by encoding the first summation result using two's complement notation.
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