| CPC G11C 7/1066 (2013.01) [G11C 7/1063 (2013.01); G11C 7/109 (2013.01); G11C 7/1093 (2013.01)] | 20 Claims |
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1. A memory system, comprising:
a plurality of pads connected to a memory device, the memory device being configured to receive a data signal using first to fourth clock output signals, the first to fourth clock output signals having different phases;
a data transmission/reception circuit configured to input and output the data signal to a data pad among the plurality of pads, the data transmission/reception circuit including a data delay cell configured to adjust a phase of the data signal;
a clock output circuit configured to generate first to fourth clock input signals and output the first to fourth clock output signals to a plurality of clock pads among the plurality of pads, the clock output circuit including first to fourth clock delay cells, the first to fourth clock delay cells being configured to receive the first to fourth clock input signals, adjust phases of the first to fourth clock input signals, and produce the first to fourth clock output signals having the different phases; and
a controller configured to:
adjust, based upon the phase of the first clock output signal, the phases of the second to fourth clock output signals using the second to fourth clock delay cells; and
after adjusting the phases of the second to fourth clock output signals, adjust a phase of the data signal using the data delay cell to align a center of an eye opening of the data signal with rising edges of the first to fourth clock output signals in a sampling circuit.
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