	US 12,205,651 B2
	Method for accessing memory cells, corresponding circuit and data storage device
Gianbattista Lo Giudice, Pedara (IT); and Antonino Conte, Tremestieri Etneo (IT)
Assigned to STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed by STMicroelectronics S.r.I., Agrate Brianza (IT)
Filed on Sep. 8, 2022, as Appl. No. 17/940,753.
Claims priority of application No. 102021000024365 (IT), filed on Sep. 22, 2021.
Prior Publication US 2023/0087074 A1, Mar. 23, 2023
Int. Cl. G11C 16/04 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01)

CPC G11C 16/24 (2013.01) [G11C 16/26 (2013.01)]

20 Claims

8. A circuit, comprising:

a sense amplifier circuit couplable to memory cells in an array of memory cells storing respective data signals, each memory cell in the array of memory cells having a first node selectively couplable to respective bitline branches in a first set of bitline branches and a second node selectively couplable to respective bitline branches in a second set of bitline branches, the first set of bitline branches and the second set of bitline branches having at least one bitline capacitance configured to store a bias level of charge in response to being charged, the sense amplifier circuit configured to:

select a first memory cell in the array of memory cells,

couple the first node of the first memory cell to a respective bitline branch in the first set of bitline branches,

couple the second node of the first memory cell to a respective bitline in the second set of bitline branches, and

detect a variation in a level of charge stored in the bitline capacitance with respect to the bias level of charge, the variation in the level of charge being indicative of a data signal stored in the first memory cell;

a pre-charge circuit comprising an access capacitor referenced to ground;

a power supply circuit configured to have a bias voltage level, the access capacitor having a node selectively couplable to the power supply circuit; and

a control circuit coupled to the pre-charge circuit and the sense amplifier circuit, the control circuit configured to operate the pre-charge circuit to:

couple the power supply circuit to the access capacitor,

apply a bias voltage level to the access capacitor such that a corresponding bias level of charge is charged on the access capacitance,

terminating the application of the bias voltage level to the access capacitor,

wherein the control circuit is further configured to operate the sense amplifier circuit to:

couple the access capacitor to the first set of bitline branches and the second set of bitline branches,

charge the bitline capacitance to the bias level of charge, and

decouple the access capacitor from the bitline capacitance.