	US 12,205,641 B2
	Dynamically boosting read voltage for a memory device
Nicola Ciocchini, Boise, ID (US); and Andrea Gotti, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 7, 2022, as Appl. No. 17/834,702.
Application 17/834,702 is a continuation of application No. 17/101,846, filed on Nov. 23, 2020, granted, now 11,373,705.
Prior Publication US 2022/0301623 A1, Sep. 22, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 13/00 (2006.01); H10N 70/00 (2023.01)

CPC G11C 13/004 (2013.01) [G11C 13/003 (2013.01); G11C 13/0069 (2013.01); H10N 70/021 (2023.02); H10N 70/063 (2023.02); H10N 70/826 (2023.02); H10N 70/882 (2023.02); G11C 2013/0045 (2013.01)]

18 Claims

1. A device comprising:

a memory array having memory cells;

a resistor; and

a controller configured to:

determine a characteristic of the resistor;

select, based on the characteristic, a read voltage;

read one or more of the memory cells using the read voltage; and

a counter configured to count write operations performed for at least a portion of the memory cells, wherein the write operation for the resistor is performed in response to determining that the counter has reached a limit.