CPC G11C 11/4096 (2013.01) [G11C 11/4085 (2013.01); G11C 11/4094 (2013.01); H03K 19/01742 (2013.01)] | 14 Claims |
1. A BNN circuit, comprising a multi-level neural network layer, wherein each level of the neural network layer of the multi-level neural network layer comprises:
a plurality of memory cell array groups arranged in parallel in a second direction;
wherein each memory cell array group among the plurality of memory cell array groups comprises:
a plurality of symmetric memory cells, arranged in a first direction for storing a weight value 1 or 0; and
an interface module arranged at one end of each memory cell array group, and configured for an input and an output of each memory cell array group,
wherein the interface module comprises:
a first inverter;
a second inverter connected to the first inverter in series and configured to correct an output waveform to a high level and/or a low level binarization,
wherein the interface module further comprises:
a third inverter, wherein one end of the third inverter is connected to a working voltage VDD, and another end of the third inverter is connected to a VGND, an input end of the third inverter is connected to an output end of the second inverter, and an output end of the third inverter is connected to a complementary word line of a next level neural network layer adjacent to the each level of the neural network layer.
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