US 12,205,017 B2
Method and apparatus for defect-tolerant memory-based artificial neural network
Win-San Khwa, Hsin-Chu (TW); Yu-Der Chih, Hsin-Chu (TW); Yi-Chun Shih, Taipei (TW); and Chien-Yin Liu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Aug. 8, 2023, as Appl. No. 18/231,769.
Application 18/231,769 is a continuation of application No. 17/883,594, filed on Aug. 8, 2022, granted, now 11,797,831.
Application 17/883,594 is a continuation of application No. 16/542,049, filed on Aug. 15, 2019, granted, now 11,461,623.
Claims priority of provisional application 62/747,277, filed on Oct. 18, 2018.
Prior Publication US 2023/0385623 A1, Nov. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/54 (2006.01); G06N 3/063 (2023.01); G06N 3/08 (2023.01); G11C 29/04 (2006.01); G11C 7/10 (2006.01)
CPC G06N 3/063 (2013.01) [G06N 3/08 (2013.01); G11C 11/54 (2013.01); G11C 29/04 (2013.01); G11C 7/1006 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving a first pattern of a plurality of memory cells;
receiving a second pattern of the plurality of memory cells;
determining at least one memory cell of the plurality of memory cells according to the first pattern and the second pattern;
switching input data of the at least one memory cell of the memory cell array;
performing a calculation using the input data stored in the plurality of memory cells; and
switching output data of at least one memory cell of the plurality of memory cells so as to determine values on first neurons of a first layer of a neural network.