US 12,204,909 B2
Direct swap caching with zero line optimizations
Ishwar Agarwal, Redmond, WA (US); George Chrysos, Portland, OR (US); Oscar Rosell Martinez, Barcelona (ES); and Yevgeniy Bak, Redmond, WA (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Nov. 7, 2023, as Appl. No. 18/503,869.
Application 18/503,869 is a continuation of application No. 17/718,920, filed on Apr. 12, 2022, granted, now 11,847,459.
Prior Publication US 2024/0103876 A1, Mar. 28, 2024
Int. Cl. G06F 12/02 (2006.01); G06F 9/38 (2018.01); G06F 9/445 (2018.01); G06F 9/50 (2006.01); G06F 12/0815 (2016.01)
CPC G06F 9/3816 (2013.01) [G06F 9/44505 (2013.01); G06F 9/5016 (2013.01); G06F 9/505 (2013.01); G06F 12/0815 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for managing a system having a system level cache, a near memory, and a far memory, wherein cache lines associated with the system level cache can be swapped between the near memory and the far memory, the method comprising:
receiving a write request from a requestor to write non-zero data corresponding to an address; and
prior to writing the non-zero data:
analyzing a first metadata portion to determine whether a current cache line stored at the address in the near memory is guaranteed to be in the system level cache, and
analyzing a second metadata portion to determine whether a data portion associated with another cache line swappable with the current cache line comprises all zeros.