	US 12,204,833 B2
	System and method to generate a network-on-chip (NoC) description using incremental topology synthesis
Moez Cherif, Santa Cruz, CA (US); and Benoit De Lescure, Campbell, CA (US)
Assigned to ARTERIS, INC., Campbell, CA (US)
Filed by ARTERIS, INC., Campbell, CA (US)
Filed on Sep. 5, 2023, as Appl. No. 18/242,504.
Application 18/242,504 is a continuation of application No. 17/239,693, filed on Apr. 26, 2021, granted, now 11,748,535, issued on Sep. 5, 2023.
Application 17/239,693 is a continuation of application No. 16/728,185, filed on Dec. 27, 2019, granted, now 10,990,724, issued on Apr. 27, 2021.
Prior Publication US 2024/0211666 A1, Jun. 27, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/327 (2020.01); G06F 30/392 (2020.01)

CPC G06F 30/327 (2020.01) [G06F 30/392 (2020.01)]

11 Claims

1. A method for topology synthesis of a network-on-chip (NoC), the method comprising:

generating, using an design tool, an initial synthesis of the NoC based on a plurality of constraints;

providing a result based on the initial synthesis;

providing an updated plurality of constraints, wherein the updated plurality of constraints include a previous run;

generating, using the design tool, a second synthesis of the NoC based on the updated plurality of constraints; and

providing an updated result based on the second synthesis,

wherein the previous run is provided to ensure that the updated result represents a minimum change between the result and the updated result when there is a minimum change between the plurality of constraints and the updated plurality of constraints.