	US 12,204,832 B2
	Logical clock connection in an integrated circuit design
Ali S. El-Zein, Austin, TX (US); Viresh Paruthi, Austin, TX (US); Alvan Wing Ng, Austin, TX (US); Benedikt Geukes, Stuttgart (DE); Klaus-Dieter Schubert, Schoenaich (DE); Robert Alan Cargnoni, Austin, TX (US); Michael Hemsley Wood, Poughkeepsie, NY (US); Stephen Gerard Shuma, Underhill, VT (US); Wolfgang Roesner, Austin, TX (US); Chung-Lung K. Shum, Wappingers Falls, NY (US); Edward Armayor McQuade, Katonah, NY (US); and Derek E. Williams, Round Rock, TX (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Sep. 7, 2021, as Appl. No. 17/468,319.
Prior Publication US 2023/0070516 A1, Mar. 9, 2023
Int. Cl. G06F 30/327 (2020.01); G06F 30/3308 (2020.01)

CPC G06F 30/327 (2020.01) [G06F 30/3308 (2020.01)]

22 Claims

1. A method of modeling operation of an integrated circuit design in a data processing system including a processor and data storage, the method comprising:

the processor of the data processing system constructing, within the data storage, a hierarchical integrated circuit design for an integrated circuit containing millions of transistors through execution of one or more electronic design automation (EDA) tools, wherein the hierarchical integrated circuit design includes a design hierarchy including a plurality of entity instances organized hierarchically in a plurality of levels including a lower level, one or more intermediate levels, and a higher level, and wherein the constructing includes:

the processor receiving a first plurality of hardware description language (HDL) files describing the hierarchical integrated circuit design utilizing a simplified HDL syntax that is not legal for an HDL compiler, wherein a particular HDL file among the first plurality of HDL files declares, utilizing storage element declarations in the simplified HDL syntax, multiple storage element entities in an intermediate level entity at an intermediate level of the hierarchical integrated circuit design and omits specification, in the storage element declarations, of logical clock connections for the multiple storage element entities, and wherein the particular HDL file further includes an attribute declaration in the simplified HDL syntax that specifies an attribute of a logical clock applicable to all of the multiple storage element entities;

the processor processing the hierarchical integrated circuit design as described by the first plurality of HDL files to obtain a second plurality of HDL files defining the hierarchical integrated circuit design utilizing a HDL syntax legal for the HDL compiler, wherein the processing includes:

converting the storage element declarations in the simplified HDL syntax into storage element declarations in HDL syntax legal for the HDL compiler;

automatically adding logical clock connections for all of the multiple storage element entities in the hierarchical integrated circuit design based on the attribute declaration in the particular HDL file; and

automatically elaborating a port map of an entity instantiated within the intermediate level entity based on signal names referenced in the first plurality of HDL files;

the processor compiling, with the HDL compiler, the second plurality of HDL files to obtain a functional simulation model of the hierarchical integrated circuit design; and

simulating operation of the hierarchical integrated circuit design utilizing the functional simulation model.