a memory cell array including a plurality of memory cells;

a peripheral circuit configured to perform a program operation on memory cells selected from among the plurality of memory cells; and

control logic configured to control the program operation of the peripheral circuit,

wherein the control logic controls the peripheral circuit to precharge bit lines respectively coupled to the selected memory cells to different voltage levels during a verify operation included in the program operation,

wherein the control logic:

determines a first memory cell which has a threshold voltage lower than a verify voltage among the selected memory cells to be programmed to a program state corresponding to the verify voltage based on a result of a previous verify operation which is performed before the verify operation using the verify voltage; and

controls the peripheral circuit to precharge a bit line coupled to the first memory cell to a first level and precharge bit lines coupled to remaining memory cells other than the first memory cell, among the selected memory cells, to a second level lower than the first level.