| CPC G06F 12/0238 (2013.01) [G06F 1/30 (2013.01); G06F 9/30047 (2013.01); G06F 12/0891 (2013.01); G06F 12/0895 (2013.01); G06F 2212/466 (2013.01)] | 18 Claims |
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1. A method comprising:
receiving, via a coherent link and at a device of an integrated circuit system, a cache line comprising a destination address;
determining, via the device, a type of memory or storage associated with the destination address as persistent or non-persistent;
tagging the cache line with metadata in a manner indicating the type of memory or storage associated with the destination address;
receiving a power fail signal at the integrated circuit system;
in response to receiving the power fail signal, to the cache line comprising a memory write request, and to the tagging indicating that the type of memory or storage associated with the destination address is persistent, selectively committing the cache line to persistent memory; and
in response to receiving the power fail signal and to the tagging indicating that the type of memory or storage associated with the destination address is non-persistent, selectively refraining from committing the cache line to volatile memory.
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