US 12,204,425 B2
Debug for multi-threaded processing
Niraj Nandan, Plano, TX (US); Hetul Sanghvi, Murphy, TX (US); Mihir Mody, Bangalore (IN); Gary Cooper, Oakmont, PA (US); and Anthony Lell, San Antonio, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Sep. 7, 2023, as Appl. No. 18/243,421.
Application 18/243,421 is a continuation of application No. 17/462,046, filed on Aug. 31, 2021, granted, now 11,789,836.
Application 17/462,046 is a continuation of application No. 16/236,745, filed on Dec. 31, 2018, granted, now 11,144,417, issued on Oct. 12, 2021.
Prior Publication US 2023/0418718 A1, Dec. 28, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/00 (2006.01); G06F 9/48 (2006.01); G06F 11/22 (2006.01); G06F 11/273 (2006.01); G06F 13/16 (2006.01); G06F 13/28 (2006.01)
CPC G06F 11/2733 (2013.01) [G06F 9/4843 (2013.01); G06F 11/2242 (2013.01); G06F 13/1668 (2013.01); G06F 13/28 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a set of schedulers, wherein each subset of the set of schedulers is configured to schedule a corresponding pipeline of a set of pipelines to execute a respective portion of instructions, and wherein the set of pipelines respectively comprises a set of hardware resources; and
a debug control unit configured to control a first subset of schedulers of the set of schedulers to cause a first pipeline of the set of pipelines corresponding to the first subset of schedulers to perform a debug operation associated with the respective portion of instructions of the first pipeline independently of a remainder of the set of pipelines.