	US 12,204,408 B2
	Memory tiering techniques in computing systems
Ishwar Agarwal, Redmond, WA (US); George Zacharias Chrysos, Portland, WA (US); and Oscar Rosell Martinez, Barcelona (ES)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Jan. 13, 2023, as Appl. No. 18/154,164.
Application 18/154,164 is a continuation of application No. 17/371,422, filed on Jul. 9, 2021, granted, now 11,599,415.
Prior Publication US 2023/0143375 A1, May 11, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G06F 3/06 (2006.01); G06F 11/14 (2006.01); G06F 12/0811 (2016.01)

CPC G06F 11/1068 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/067 (2013.01); G06F 3/0679 (2013.01); G06F 11/1435 (2013.01); G06F 12/0811 (2013.01)]

20 Claims

1. A computer-implemented method of memory management, the method comprising:

receiving a request from a processor to read data corresponding to a system memory section from a cache of the processor;

retrieving, from a first section in a first memory, data and metadata, the metadata encoding data location information of multiple system memory sections in the first section of the first memory, a second section of the first memory, and one or more additional sections in a second memory;

analyzing the data location information in the retrieved metadata to determine that the first section in the first memory currently contains data corresponding to the system memory section in the received request; and

in response to determining that the first section in the first memory currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the first section in the first memory to the processor in response to the received request.