US 12,204,364 B2
Systems and methods for multi-phase clock generation
Wei Chih Chen, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Aug. 9, 2023, as Appl. No. 18/446,869.
Application 18/446,869 is a continuation of application No. 18/064,308, filed on Dec. 12, 2022, granted, now 11,768,516.
Application 18/064,308 is a continuation of application No. 17/080,920, filed on Oct. 27, 2020, granted, now 11,550,354, issued on Jan. 10, 2023.
Claims priority of provisional application 62/977,777, filed on Feb. 18, 2020.
Prior Publication US 2024/0019891 A1, Jan. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/08 (2006.01); H03K 19/21 (2006.01); H03L 7/085 (2006.01); H03L 7/099 (2006.01); H03M 1/66 (2006.01)
CPC G06F 1/08 (2013.01) [H03K 19/21 (2013.01); H03L 7/085 (2013.01); H03L 7/0998 (2013.01); H03M 1/66 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A clock generator comprising:
a phase error corrector configured to receive intermediate signals and to generate N clock output signals, wherein a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees and the phase error corrector is further configured to receive a feedback signal and to reduce phase errors among the clock output signals based on the feedback signal, wherein the phase error corrector includes a phase corrector transistor having a gate terminal configured to receive one of the intermediate signals.