| CPC G01R 31/3177 (2013.01) [G01R 31/318541 (2013.01); G01R 31/318552 (2013.01); G01R 31/318594 (2013.01); H03K 3/0372 (2013.01); H03K 19/21 (2013.01)] | 17 Claims |
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1. A circuit, comprising:
a plurality of cascaded flip-flops including:
a set of first flip-flops, wherein a first flip-flop of the set of first flip-flops is configured to:
receive a functional input or a test input;
receive a clock signal; and
trigger operation to update an output state of the first flip-flop based on a clock edge of the clock signal,
a set of second flip-flops different than the set of first flip-flops, wherein a second flip-flop of the set of second flip-flops is configured to:
receive the functional input or the test input;
receive the clock signal;
invert the clock signal to produce an inverted clock signal; and
trigger operation to update an output state of the second flip-flop based on a clock edge of the inverted clock signal.
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