| CPC G01R 31/2884 (2013.01) [G01R 31/31715 (2013.01); G01R 31/318511 (2013.01)] | 20 Claims |
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1. A memory device comprising:
a buffer die including a test circuit; and
a plurality of core dies stacked on the buffer die and connected to the buffer die through a plurality of through-silicon vias,
wherein the buffer die comprises:
a plurality of master test pads configured to receive a plurality of master test operation signals provided by an external device;
a mode register configured to set a bit signal allocated to indicate whether a test access signal pad among the plurality of master test pads is being used; and
a master test circuit comprising:
a master toggle detection circuit configured to detect a toggling of a first master test operation signal among the plurality of master test operation signals in an interval, and generate a master toggle detection signal based on the toggling of the first master test operation signal; and
a test enable signal generation circuit configured to:
receive the master toggle detection signal,
generate an internal master test enable signal in response to the master toggle detection signal and the bit signal indicating that the test access signal pad is not being used, and
transmit the internal master test enable signal to at least one of the plurality of core dies through at least one of the plurality of through-silicon vias.
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