US 11,877,447 B2
Manufacturing method of semiconductor structure and flash memory
Yao-Ting Tsai, Taichung (TW); Hsiu-Han Liao, Taichung (TW); and Che-Fu Chuang, Taichung (TW)
Assigned to Winbond Electronics Corp., Taichung (TW)
Filed by Winbond Electronics Corp., Taichung (TW)
Filed on Apr. 10, 2023, as Appl. No. 18/297,659.
Application 18/297,659 is a division of application No. 17/376,079, filed on Jul. 14, 2021, granted, now 11,678,484.
Claims priority of application No. 109125446 (TW), filed on Jul. 28, 2020.
Prior Publication US 2023/0255026 A1, Aug. 10, 2023
Int. Cl. H01L 21/00 (2006.01); H10B 41/42 (2023.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H10B 41/30 (2023.01)
CPC H10B 41/42 (2023.02) [H01L 29/66825 (2013.01); H01L 29/7883 (2013.01); H10B 41/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A manufacturing method of a semiconductor structure, comprising:
providing a substrate having a peripheral region and a memory region;
forming a plurality of first isolation structures in the substrate in the peripheral region, so that a first active area is defined between the first isolation structures;
forming an oxide layer on the substrate in the first active area, wherein a top surface of the oxide layer is covered by the first isolation structures, and an opening is defined in the oxide layer and the first isolation structures covering the oxide layer and exposes a part of the substrate; and
forming a gate structure on the substrate in the first active area, wherein steps of forming the gate structure comprises:
forming a gate dielectric layer on the substrate in the opening, so that the oxide layer is located around the gate dielectric layer; and
forming a gate on the gate dielectric layer, wherein a width of a bottom surface of the gate is less than a width of a top surface of the first active area.