US 11,877,437 B2
Semiconductor device with low-k spacer
Beom Ho Mun, Gyeonggi-do (KR); Eun Jeong Kim, Gyeonggi-do (KR); Jong Kook Park, Gyeonggi-do (KR); Seung Mi Lee, Gyeonggi-do (KR); Ji Won Choi, Gyeonggi-do (KR); Kyoung Tak Kim, Gyeonggi-do (KR); and Yun Hyuck Ji, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Jul. 13, 2021, as Appl. No. 17/374,578.
Claims priority of application No. 10-2020-0105302 (KR), filed on Aug. 21, 2020; and application No. 10-2021-0013422 (KR), filed on Jan. 29, 2021.
Prior Publication US 2022/0059543 A1, Feb. 24, 2022
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/315 (2023.02) [H10B 12/0335 (2023.02); H10B 12/34 (2023.02); H10B 12/482 (2023.02)] 28 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a bit line structure including a bit line contact plug, a bit line, and a bit line hard mask that are sequentially stacked over a substrate;
a storage node contact plug that is spaced apart from the bit line structure;
a conformal spacer that is positioned between the bit line and the storage node contact plug and includes a low-k material; and
a seed liner that is positioned between the conformal spacer and the bit line,
wherein the seed liner is thinner than the conformal spacer.