US 11,877,082 B2
Image sensor employing avalanche diode
Tso-Sheng Tsai, Hsin-Chu County (TW)
Filed by PIXART IMAGING INC., Hsin-Chu County (TW)
Filed on Nov. 15, 2022, as Appl. No. 17/986,947.
Application 17/378,843 is a division of application No. 16/872,626, filed on May 12, 2020, granted, now 11,102,439, issued on Aug. 24, 2021.
Application 16/872,626 is a division of application No. 16/258,673, filed on Jan. 28, 2019, granted, now 10,715,756, issued on Jul. 14, 2020.
Application 17/986,947 is a continuation of application No. 17/378,843, filed on Jul. 19, 2021, granted, now 11,575,854.
Prior Publication US 2023/0077016 A1, Mar. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H04N 25/75 (2023.01); H01L 27/146 (2006.01); H04N 25/76 (2023.01); H01L 31/107 (2006.01)
CPC H04N 25/75 (2023.01) [H01L 27/14612 (2013.01); H01L 27/14643 (2013.01); H04N 25/76 (2023.01); H01L 31/107 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An image sensor, comprising:
a pixel array comprising a plurality of pixel circuits arranged in a matrix, each of the pixel circuits comprising:
an avalanche diode having an anode and a cathode, the cathode being connected to a positive bias voltage;
a resistive transistor, a drain of the resistive transistor connected to the anode of the avalanche diode, and a gate of the resistive transistor configured to receive a fixed voltage signal;
a first switch transistor, a drain of the first switch transistor connected to a source of the resistive transistor, a gate of the first switch transistor configured to receive an exposure signal, and a source of the first switch transistor connected to a ground voltage;
a pull down transistor, a gate of the pull down transistor connected to the anode of the avalanche diode, and a source of the pull down transistor connected to the ground voltage; and
a second switch transistor, a gate of the second switch transistor configured to receive the exposure signal, a source of the second switch transistor connected to a drain of the pull down transistor, and a drain of the second switch transistor configured to generate an output voltage; and
a plurality of readout lines each being coupled to the drain of the second switch transistor of each pixel circuit of one pixel circuit column to output the output voltage.