CPC H04L 27/2628 (2013.01) [H04L 25/03159 (2013.01); H04L 27/2605 (2013.01); H04L 27/2614 (2013.01)] | 20 Claims |
1. A system for modulating a signal, comprising:
a transceiver, and
a processor in communication with the transceiver, the processor:
receiving an input signal from the transceiver; and
modulating the input signal to form Dirichlet kernels in a time domain to generate an offset Dirichlet kernel output time array, each Dirichlet kernel having a main lobe and a plurality of side lobes,
wherein modulating the input signal suppresses a peak to average power ratio of the offset Dirichlet kernel output time array by reducing the plurality of side lobes of each Dirichlet kernel and respective amplitudes of the side lobes, and wherein, in modulating the input signal, the processor inserts a spectral guard interval having a duration exceeding a largest delay spread interval between spectral replicates of the input signal in an M-point input frequency array.
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