US 11,876,649 B2
Hybrid analog/digital equalizer architecture for high-speed receiver
Luke Wang, San Jose, CA (US); Benjamin Smith, Ottawa (CA); Basel Alnabulsi, Ottawa (CA); Stephane Dallaire, Gatineau (CA); Simon Forey, Earls Barton (GB); Karthik Raviprakash, San Jose, CA (US); Praveen Prabha, Lake Forest, CA (US); and Benjamin T. Reyes, Cordoba (AR)
Assigned to Marvell Asia Pte Ltd, Singapore (SG)
Filed by Marvell Asia Pte Ltd, Singapore (SG)
Filed on Jan. 20, 2022, as Appl. No. 17/648,440.
Claims priority of provisional application 63/230,530, filed on Aug. 6, 2021.
Prior Publication US 2023/0037860 A1, Feb. 9, 2023
Int. Cl. H04L 25/03 (2006.01); H04L 25/02 (2006.01)
CPC H04L 25/03076 (2013.01) [H04L 25/0232 (2013.01); H04L 2025/03433 (2013.01); H04L 2025/03605 (2013.01)] 17 Claims
OG exemplary drawing
 
1. Equalization circuitry for a data channel in an integrated circuit device, the equalization circuitry comprising:
an analog equalization circuitry portion coupled to the data channel, including interleaver circuitry configured to disperse incoming signals to a plurality of interleaved equalization blocks, each interleaved equalization block in the plurality of equalization blocks comprising a feed-forward equalization circuitry portion, a decision-feedback equalization circuitry portion and a decision circuitry portion; and
a digital signal processing circuitry portion downstream of the analog equalization circuitry portion, the digital signal processing circuitry portion being configured to generate control signals to control the analog equalization circuitry portion, the digital signal processing circuitry portion also including a digital equalization circuitry portion configured to operate on an output of the analog equalization circuitry portion; wherein:
each respective interleaved equalization block in the plurality of equalization blocks comprises a probe slicer configured to output estimated signal properties for use by the digital signal processing circuitry portion, the estimated signal properties excluding effects of analog circuitry in the respective interleaved equalization block.