US 11,876,622 B2
LDPC encoder and decoder for multi-mode higher speed passive optical networks
Rainer Strobel, Munich (DE); and Santhosh K. Vanaparthy, Santa Clara, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 15, 2021, as Appl. No. 17/201,032.
Claims priority of provisional application 62/992,623, filed on Mar. 20, 2020.
Prior Publication US 2021/0297182 A1, Sep. 23, 2021
Int. Cl. H04B 10/516 (2013.01); H04B 10/69 (2013.01); H04L 1/00 (2006.01); H04B 10/27 (2013.01); H04B 10/50 (2013.01); H04B 10/66 (2013.01)
CPC H04L 1/0061 (2013.01) [H04B 10/27 (2013.01); H04B 10/50 (2013.01); H04B 10/516 (2013.01); H04B 10/66 (2013.01); H04B 10/69 (2013.01); H04L 1/0042 (2013.01); H04L 1/0047 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A forward-error-correction (FEC) encoder that is suitable for generating FEC data for use with hard-decision input at a receiver and for use with soft-decision input at the receiver, comprising:
Low-Density Parity-Check (LDPC) parity encoder circuitry configured to generate parity bits from payload bits using an LDPC code; and
puncturing/shortening circuitry configured to puncture and/or shorten the parity bits and/or the payload bits to generate the FEC data,
wherein the LDPC parity encoder circuitry and the puncturing/shortening circuitry are configured to generate the FEC data either:
a) using a single LDPC code that is suitable for use with soft-decision input and hard-decision input at the receiver, wherein the LDPC parity encoder circuitry and the puncturing/shortening circuitry are configured to generate the FEC data using the same LDPC code for use with hard-decision input at the receiver and for use with soft-decision input at the receiver, and the FEC data is generated using a single LDPC code that uses a first set of puncturing bits and/or a first set of shortening bits for use with soft-decision input at the receiver and a second set of puncturing bits and/or a second set of shortening bits for use with hard-decision input at the receiver, or
b) using one of two LDPC codes that are suitable for soft-decision input and hard-decision input, respectively, wherein one of the two LDPC codes is used for use with soft-decision input at the receiver and the other of the two LDPC codes is used for use with hard-decision input at the receiver.