US 11,876,535 B1
Memory controller and method for controlling data in decoding pipeline
Shiuan-Hao Kuo, New Taipei (TW)
Assigned to SILICON MOTION, INC., Jhubei (TW)
Filed by Silicon Motion, Inc., Jhubei (TW)
Filed on Sep. 19, 2022, as Appl. No. 17/933,190.
Claims priority of application No. 111131087 (TW), filed on Aug. 18, 2022.
Int. Cl. H03M 13/00 (2006.01); H03M 13/11 (2006.01); H03M 13/15 (2006.01)
CPC H03M 13/1111 (2013.01) [H03M 13/1128 (2013.01); H03M 13/1575 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A memory controller, for use in a data storage device, wherein a low-density parity-check (LDPC) decoding procedure performed by the memory controller comprises an initial phase, a decoding phase, and an output phase in sequence, the memory controller comprising:
a memory-index control circuit, configured to control data access of a variable-node memory; and
a decoder, comprising a decoding pipeline to perform the decoding phase of the LDPC decoding procedure,
wherein after the data storage device is booted up, the decoder reads a plurality of first codewords from the variable-node memory using a first order via the memory-index control circuit for LDPC decoding,
wherein in response to the decoder determining that a specific codeword among the first codewords has decoding failure, the decoder is reset to read a plurality of second codewords from the variable-node memory using a second order via the memory-index control circuit for LDPC decoding,
wherein the first order is different from the second order.