US 11,876,522 B2
Duty-cycle corrector circuit
WeiShuo Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Dec. 23, 2022, as Appl. No. 18/146,287.
Application 18/146,287 is a continuation of application No. 17/538,825, filed on Nov. 30, 2021, granted, now 11,539,369.
Claims priority of provisional application 63/185,027, filed on May 6, 2021.
Prior Publication US 2023/0238966 A1, Jul. 27, 2023
Int. Cl. H03L 7/07 (2006.01); H03L 7/095 (2006.01); H03L 7/081 (2006.01)
CPC H03L 7/07 (2013.01) [H03L 7/0816 (2013.01); H03L 7/095 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A duty-cycle (DC) corrector circuit, comprising:
a delay-locked loop (DLL) circuit; and
a duty-cycle correction (DCC) circuit connected to the DLL circuit, wherein the DCC circuit comprises:
a duty adjusting (DA) circuit operable to receive a clock_in signal and output a delayed first signal, the DA circuit further operable to adjust a duty cycle of the delayed first signal based on receipt of a duty control signal;
a pulse generator (PG) circuit operably connected to the DA circuit, the PG circuit operable to receive the delayed first signal and a delayed second signal and output a first pulse signal and a second pulse signal.