CPC H03L 7/07 (2013.01) [H03L 7/0816 (2013.01); H03L 7/095 (2013.01)] | 20 Claims |
1. A duty-cycle (DC) corrector circuit, comprising:
a delay-locked loop (DLL) circuit; and
a duty-cycle correction (DCC) circuit connected to the DLL circuit, wherein the DCC circuit comprises:
a duty adjusting (DA) circuit operable to receive a clock_in signal and output a delayed first signal, the DA circuit further operable to adjust a duty cycle of the delayed first signal based on receipt of a duty control signal;
a pulse generator (PG) circuit operably connected to the DA circuit, the PG circuit operable to receive the delayed first signal and a delayed second signal and output a first pulse signal and a second pulse signal.
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